MOSFET Threshold Voltage Calculator

How MOSFET Threshold Voltage and the Body Effect Work

The threshold voltage (V_T) of a MOSFET is the gate-to-source voltage at which the channel just reaches strong inversion — the point where a continuous conducting path of minority carriers forms between source and drain. Below V_T the device is essentially off (aside from small subthreshold leakage); above it, drain current turns on and grows with (V_GS − V_T) in saturation. V_T is not a single fixed number, though: it depends on the voltage between the source and the body (substrate) terminal, V_SB. This calculator implements the classic body-effect equation (also called the substrate-bias or back-gate effect), the same first-order model used in SPICE Level-1/Level-2 transistor models: V_T = V_T0 + γ(√(2φ_F + V_SB) − √(2φ_F)).

Reading the body-effect equation

• V_T0 is the threshold voltage measured with the source tied directly to the body (V_SB = 0) — the value you'd find on a datasheet or SPICE model card.
• γ (gamma) is the body-effect coefficient, γ = √(2qε_si N_A)/C_ox, where N_A is the substrate (or well) doping concentration and C_ox = ε_ox/t_ox is the gate-oxide capacitance per unit area. It sets how strongly V_T responds to body bias.
• 2φ_F is the surface potential at strong inversion — twice the bulk Fermi potential φ_F = (kT/q) ln(N_A/n_i) — and is set by the substrate doping and temperature, typically 0.6–0.9 V at room temperature.
• V_SB is the reverse bias between source and body. Physically, raising V_SB widens the depletion region under the gate, so more gate charge — and hence a higher V_GS — is needed to reach strong inversion, which is why V_T increases (in magnitude) as V_SB increases.

Practical notes

• The equation is valid when 2φ_F + V_SB ≥ 0; for NMOS this normally means V_SB ≥ 0 (source at or above body potential), since a strongly negative V_SB would forward-bias the source-body diode outside normal operation.
• The body effect matters most when the source of a transistor is not tied to its own body — stacked (cascode) NMOS stages, pass-transistor logic, source followers, and DRAM bit-line transistors are common examples.
• For PMOS devices the same square-root-difference form applies (with N_D well doping in place of N_A), but V_T0 is negative and most SPICE models flip the sign convention on V_SB — this calculator computes the magnitude form shared across NMOS and PMOS documentation.
• Because γ and 2φ_F come from process parameters (doping, oxide thickness), they are usually constants for a given fabrication process — only V_SB varies with the circuit's operating point.

Frequently Asked Questions