LFSR Calculator

Enter a register length, seed, and tap positions to step a Fibonacci linear feedback shift register (LFSR) and get its output bit sequence, cycle period, and final state.

Quick Facts

Feedback rule
new bit = XOR of tapped bits
Each clock cycle, the tapped bits are XORed together and loaded into the register as it shifts.
Maximum period
2ⁿ − 1
An n-bit LFSR can pass through at most 2ⁿ − 1 nonzero states before repeating.
Maximal-length (m-sequence)
Needs a primitive polynomial
Only specific tap sets reach the full 2ⁿ − 1 period; most tap sets produce shorter cycles.

Your Results

Calculated
Output Bit Sequence
-
Bits shifted out, in order
Cycle Period
-
Steps until the register returns to the seed state
Final Register State
-
State after the requested output bits
Sequence Type
-
Maximal-length (m-sequence) or shorter cycle

Ready

Enter a register length, seed, and taps, then press Calculate.

How the LFSR Calculator Works

A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function — here, an XOR — of some of its previous bits, called taps. This calculator implements the standard Fibonacci (external-XOR) LFSR: on each clock cycle, the tapped bits are XORed together to form a feedback bit, every bit shifts one position toward the output end, the bit that shifts out becomes the next bit of the output sequence, and the feedback bit is loaded into the newly empty position at the other end.

The feedback and shift rule

Number the register's bits 1 through n from left (most significant, entry point) to right (least significant, output point). A tap set T ⊆ {1, …, n} — which must include position n — defines the feedback bit as f = b₍t₁₎ ⊕ b₍t₂₎ ⊕ … for every tap position in T. Each clock cycle, the rightmost bit (position n) is read off as the next output bit, every other bit shifts one place to the right, and f is written into position 1. This is exactly the update rule implemented by the calculator above. The tap set corresponds to a characteristic polynomial over GF(2); taps at positions 4 and 3, for example, correspond to x⁴ + x³ + 1.

Period and maximal-length sequences

Because the feedback function is linear and always includes position n, the state transition is a bijection on the register's 2ⁿ possible values, with the all-zero state fixed in place. A nonzero seed therefore cycles indefinitely through nonzero states only, and the cycle length (period) always divides evenly into the register's state space, topping out at 2ⁿ − 1. When the tap set corresponds to a primitive polynomial over GF(2), every nonzero seed produces a single cycle of the maximum possible length 2ⁿ − 1 — this is called a maximal-length sequence or m-sequence, and it is the configuration used in most pseudo-noise (PN) generators, CRC circuits, and stream ciphers. Other tap sets split the 2ⁿ − 1 nonzero states into several shorter cycles instead of one long one.

Practical notes

  • Seed must be nonzero: an all-zero state is a fixed point — its feedback is always 0, so the register never changes. This calculator rejects an all-zero seed.
  • Position n must be tapped: the rightmost (highest-numbered) position must be included in the tap set for the transition to be invertible; leaving it out can make bits collide onto the same next state instead of forming a clean cycle.
  • Known maximal tap sets: commonly cited primitive tap sets (numbered 1 = leftmost, n = rightmost, as used here) include {3,2} for n = 3, {4,3} for n = 4, {5,3} for n = 5, and {7,6} for n = 7 — each gives the full 2ⁿ − 1 period for any nonzero seed.
  • Applications: LFSRs generate pseudo-random bit streams, scramble/whiten data in communications links, drive built-in self-test (BIST) circuits, compute CRC checksums, and form building blocks inside stream ciphers.

Frequently Asked Questions

What is a linear feedback shift register (LFSR)?
An LFSR is a shift register whose next input bit is the XOR of specific bits (the taps) from its current state. Each clock cycle it shifts all bits one position, loads the XOR result into the empty position, and outputs the bit that shifted out, producing a deterministic pseudo-random bit sequence.
How do I choose tap positions for a maximal-length sequence?
The tap positions must correspond to a primitive polynomial over GF(2) of degree n. Well-known examples include taps 3,2 for a 3-bit register, 4,3 for a 4-bit register, 5,3 for a 5-bit register, and 7,6 for a 7-bit register; using these taps with any nonzero seed produces the full 2ⁿ − 1 period.
Why can't the seed be all zeros?
An all-zero state feeds back an XOR of zeros, so the register stays at zero forever. Any nonzero seed instead cycles through nonzero states only, because the LFSR's linear feedback transition is a bijection when the highest tap position is included.
What does "maximal-length" or "m-sequence" mean?
A maximal-length sequence (m-sequence) is produced when the tap set corresponds to a primitive polynomial: the LFSR visits all 2ⁿ − 1 nonzero states exactly once before repeating, which is the longest possible period for that register length.